ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

Designs with LogicBIST exhibit random pattern resistance because of the random nature of LBIST vectors, thus leading to low fault coverage. To handle this, we insert test points with the help of ...