Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when ...

One of the greatest struggles for verification teams today is deciding on the right approach when a system-on-chip (SoC) is assembled and ready for verification. Each of the blocks has undergone ...

Coping with the endless growth in chip size and complexity requires innovative electronic design automation (EDA) solutions at every stage of the development process. Better algorithms, increased ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

Mentor Graphics has released a version of ModelSim that integrates the technology the company recently acquired with the purchase of 0-In Design Automation. ModelSim 6.0 offers standards-based support ...