EDN

Synthesis tool links MATLAB with ASIC, FPGA designs

MILPITAS, Calif. — AccelChip has crafted a DSP synthesis tool that converts algorithms developed in MATLAB into synthesizable RTL that can be used during the design of FPGAs, ASICs and structured ...
EDN

An FPGA-to-ASIC case study for refining smart meter design

Many embedded system designs are first implemented using FPGAs. This may be for quicker prototyping or to provide a platform for software development. Sometimes, the FPGAs will remain in the design ...
Design-Reuse

Structured ASIC Based SoC Design

Complex System-on-Chip (SoC) designs are fast becoming commonplace in today’s applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market (TTM), ...
Design-Reuse

PCI Express Design Considerations -- RapidChip Platform ASIC vs. FPGA Design Efficiency

This paper describes the implementation differences of an IP core between FPGA and RapidChip® Platform ASIC technologies. By mapping the same complex, high-speed PCI Express core onto these two ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Electronic Design

Faraday Showcases FPGA-Go-ASIC, SONOS eFlash, and eFPGA Solutions

This article appeared in Microwaves & RF and has been published here with permission. Check out our Design Automation Conference 2023 coverage. Faraday Technology comes to Booth 2343 at DAC to discuss ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...