Semiconductor Engineering

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System

A technical paper titled “RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory” was published by researchers at ETH Zürich, KMUTNB, ...
Communications of the ACMOpinion

The Golden Rule of Big Memory: Persistence Is Not Harmful

Large-scale applications, such as generative AI, recommendation systems, big data, and HPC systems, require large-capacity ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
Semiconductor Engineering

Accelerating Off -Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path

A new technical paper titled “Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction” was published by researchers at ETH Zurich, Intel Processor Architecture ...
EDN

MRAM technologies: from space applications to unified cache memory?

Magneto-resistive random access memory (MRAM) is a non-volatile memory technology that relies on the (relative) magnetization state of two ferromagnetic layers to store binary information. Throughout ...