EDN

Avoid signal-integrity blowouts in SOC-design IP-block integration

Many small and large design teams use third-party IP (intellectual property) to accelerate SOC (system-on-chip) design by importing functional blocks, such as data converters, PLLs, Ethernet PHY ...
Semiconductor Engineering

Enabling Integration Success Using High-Speed SerDes IP

Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed ...
Semiconductor Engineering

Why Every Design IP Needs A Complete QA Methodology

Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables ...
Electronic Design

Facing The Challenge Of Adding RF And Mixed-Signal IP To SoCs

Designers must deal with multiple simulation domains, floorplanning, IP packaging, and other key issues. As CMOS technologies scale to greater densities, the ability to design and integrate complex ...
EDN

Xilinx Vivado Design Suite Accelerates Time to Integration and System-Level Design to Stay a Generation Ahead

To accelerate the creation of highly integrated, complex designs in All Programmable FPGA devices, Xilinx has delivered the early access release of the Vivado IP Integrator (IPI). Vivado IPI ...