Semiconductor Engineering

Are You Using Structural Patterns In An SLT Environment?

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...
EDN

Design for test boot camp, part 3: Advanced fault models and cell-aware test

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...