EDN

SPICE-based stochastic design of SRAM Array considering PVT variations

Seeking an internship position during the summer of 2011 in the area of Digital ASIC Design with focus on Front-end design, Verification or Layout. Obtained Bachelor’s degree in Electronics ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...
Design-Reuse

sureCore Delivers Customised Low Power SRAM for Data Intensive Designs

SHEFFIELD, England, Mar. 21, 2019 – sureCore Limited's new SureFit SRAM customization service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 ...
Design-Reuse

Embedded SRAM test and repair moves on-chip

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to ...
Electronic Design

10T SRAM Circuitry Clocks at 3.1 GHz

This file type includes high resolution graphics and schematics when applicable. Memory plays a continually more important role in digital and mixed-signal circuits, but a key for future designs is ...