EDN

Agere to pull Cadence partitioning, sign-off tool into ASIC flow

ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...
EDN

System delivers ASIC prototypes in two weeks

The HAPS-80 FPGA-based SoC/ASIC prototyping system offers a balance of simulation and emulation for reduced design time and supports up to 1.6 billion ASIC gates based on the Xilinx Virtex UltraScale ...
Business Wire

Aldec Solves ASIC Design Partitioning Challenges With HES-DVM Proto Mode

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of its HES-DVM™ ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Business Wire

Aldec Cuts ASIC Design Prototype Bring-Up Time with HES-DVM’s Automatic Partitioning Tool and Faster HDL-to-FPGA Compilation Times

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...
Electronic Design

Carefully Weigh The Tradeoffs Of Cell-Based Vs. Structured ASICs

With the emergence of 90-nm process technology, ASIC designers get to explore uncharted levels of performance and density. However, it has also unleashed a slew of challenging design-integrity issues, ...