EDN

Inheritance and polymorphism of SystemVerilog OOP for UVM verification

This is the second part in a series of introductory articles on SystemVerilog (SV) object oriented programming (OOP). In the first article, we covered the basics of the class data type and the history ...
EDN

Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.
Design-Reuse

Verification IP Reuse For Complex Networking Asics

Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity ...
Electronic Design

Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli

Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test ...
Design-Reuse

Transaction Analysis and Debug across Language Boundaries and between Abstraction Levels

Transaction analysis and debug between multiple abstraction levels is now possible with current technology. This paper will present an API and implementation for recording transactions from SystemC, C ...