ANAHEIM, Calif. — At an open meeting held Monday at the Design Automation Conference, EDA, test and silicon debug companies announced the creation of the Design-for-Debug (DFD) Consortium to address ...

AUSTIN, Texas--(BUSINESS WIRE)--NIWeek – NI (Nasdaq: NATI), the provider of a software-defined platform that helps accelerate the development and performance of automated test and automated ...

TOKYO, May 08, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic Test Engineering (TE), the newest addition to the SiConic ...

SANTA ROSA, Calif.--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that helps enterprises, service providers and governments accelerate innovation to connect ...

In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at ...

The ability to display up to ten eye diagrams simultaneously provides a high-level view of system performance during system bring-up. The multi-measurement scenario analysis capability easily lends ...

Advantest Corp. has unveiled SiConic Test Engineering (TE), the newest addition to the SiConic family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate ...

Teledyne LeCroy has introduced the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most oscilloscope-based DDR physical layer test tools on the market are ...

As Moore's Law steams ahead, the resulting rush to retool for ever-smaller geometries has led to the realization by most leading companies designing systems-on-chip that the emphasis in SoCs is on ...

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, ...