Semiconductor Engineering

Interface DRC Can Streamline Chip-Level Interface Physical Verification

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the ...
EDN

Silicon Interfaces announces the release of its new RapidIO Physical Layer Interface OpenVera Verification IP

Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program – Silicon Cores: Core to the Intelligent ...
EDN

The Challenge of Interface Verification

Designs in every industry segment are built around standard interfaces; you probably can't find a complex chip that does not have some sort of standard interface such as PCI, PCI Express, DDR-SDRAM, ...
Design-Reuse

Secrets of M-PHY Verification

We at Arrow Devices are committed to help developers build fast and robust standard interface IP. We have prepared the following actionable questionnaire and downloadable test plan for MIPI M-PHY v2.0 ...
Design-Reuse

Increased Verification Productivity through extensive Reuse

With today’s functional verification challenge outstripping the design challenge in terms of manpower, complexity and sheer time to complete, it is necessary to ensure that we reuse verification as ...