The Next Platform

Drilling Into The CCIX Coherence Standard

The past decade or so has seen some really phenomenal capacity growth and similarly remarkable software technology in support of distributed-memory systems. When work can be spread out across a lot of ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
EDN

Memory models for embedded multicore SoCs, Part 1 – Memory architecture

Editor's Note: Multicore architectures find use across a diverse range of applications thanks to their performance and efficiency. By combining several general-purpose MCU cores — or MCU cores and ...
The Next Platform

Weaving Accelerators Into The Memory Complex

In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...
Electronic Design

CCIX: Cache Coherent Interconnect for Accelerators

The Cache Coherent Interconnect for Accelerators standard, or CCIX (pronounced “see 6”), is built on PCI Express (PCIe) to provide a chip-to-chip interconnect for high-speed hardware accelerators. It ...
Semiconductor Engineering

Heterogeneous Cache Coherence Requires A Common Internal Protocol

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and ...
Science Daily

First new cache-coherence mechanism in 30 years

A fundamentally new approach to cache coherence has been released -- the first in more than three decades. Whereas with existing techniques, the directory's memory allotment increases in direct ...
EDN

Memory models for embedded multicore SoCs, Part 5 – Cache performance

Write-through: all cache memory writes are written to main memory, even if the data is retained in the cache, such as in the example in Figure 4.11. A cache line can be in two states – valid or ...
Semiconductor Engineering

Memory Architectures In AI: One Size Doesn’t Fit All

In the world of regular computing, we are used to certain ways of architecting for memory access to meet latency, bandwidth and power goals. These have evolved over many years to give us the multiple ...
Embedded

Tips for effective usage of the shared cache in multi-core architectures

While traditional single core systems employ a dedicated cache, theintroduction of multi-core platforms presents the opportunity toconsider the shared use of cache by multiple processors. Designs ...
TechRepublic

Cache-Only Memory Architecture

A Cache-Only Memory Architecture design (COMA) may be a sort of Cache-Coherent Non-Uniform Memory Access (CC- NUMA) design. not like in a very typical CC-NUMA design, in a COMA, each shared-memory ...