Redux Time Travel Debugging - Search Videos

[DVCon 2025] Debugging SystemC / HLS Models | Undo

[DVCon 2025] Debugging SystemC / HLS Models | Undo

Debugging high-level synthesis models can feel like a black box. HLS models tend to be architected to have many parallel execution units. A real design could have tens of thousands of threads. Higher parallelism means a higher probability of challenging bugs such as race conditions, deadlocks, memory corruptions, and intermittent issues. In ...

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